The invention relates to a synchronizing stage for synchronizing asynchronous signals, having a clocked input stage, an output stage and a holding stage.
A synchronizing stage of this type has the task of synchronizing an asynchronous input datum, with a clock signal. For this purpose, use is typically made of holding stages which buffer-store the input signal until it can be synchronized by a clock signal. A plurality of cascaded holding stages (a latch) are suitable. However, it is often the case that such two-stage or three-stage synchronization is not possible and it would be desirable to manage with one synchronizing stage. A single-stage configuration is known in which an input signal and a clock signal are applied to an input stage. A holding stage containing two negative feedback inverters is connected downstream of the input stage. The input of an output stage is connected downstream of the junction point between the input stage and the holding stage, the output stage providing the output signal at its output. The input and output stages are normally inverters. Difficulties can arise if the input signal and the clock signal change over simultaneously. In this case, it can happen that the input signal is not transferred to the output, because the switching speeds of the individual stages of the synchronizing stage are finite and the switching thresholds are different. So-called metastable states can arise, in which a momentary signal change takes place at the output but afterwards, on account of the parasitic physical properties of the synchronizing stage, an intrinsically false signal is present (so-called spikes). In the realization of a synchronizing stage, therefore, it is necessary to keep the probability of a metastable state low.
It is accordingly an object of the invention to provide a synchronizing stage which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which synchronizes asynchronous signals and takes up little space in an integrated semiconductor circuit and keeps the probability of metastable states low in the event of signal and clock-signal changeovers.
With the foregoing and other objects in view there is provided, in accordance with the invention, a synchronizing stage for synchronizing asynchronous signals, including a clocked input stage; an output stage; a holding stage connected serially between the clocked input stage and the output stage and being clocked in an anti-phase fashion; and a signal stage connected in parallel with a circuit formed of the input stage and the holding stage, the signal stage clocked in anti-phase with respect to the input stage.
In accordance with an added feature of the invention, the output stage is an inverter or a Schmitt triggers.
In accordance with another feature of the invention, the holding stage clocked in anti-phase receives a clock signal and an anti-phase clock signal, the anti-phase clock signal is generated by inverting the clock signal.
In accordance with an additional feature of the invention, the input stage is an inverter and/or the holding stage contains two feedback inverters.
In accordance with a concomitant feature of the invention, the signal stage contains two series-connected inverters, including an upstream inverter and a clocked downstream inverter.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a synchronizing stage, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.